Download E-books Layout Minimization of CMOS Cells (The Springer International Series in Engineering and Computer Science) PDF
By Robert L. Maziasz
The format of an built-in circuit (lC) is the method of assigning geometric form, dimension and place to the parts (transistors and connections) utilized in its fabrication. because the variety of parts in modem ICs is big, laptop aided-design (CAD) courses are required to automate the tough format strategy. earlier CAD tools are inexact or constrained in scope, and bring layouts whose quarter, and as a result production expenditures, are higher than important. This publication addresses the matter of minimizing precisely the structure sector of a huge category of uncomplicated IC buildings known as CMOS cells. First, we accurately outline the potential pursuits in quarter minimization for such cells, particularly width and peak minimization, with allowance for area-reducing reordering of transistors. We reformulate the structure challenge by way of a graph version and increase new graph-theoretic innovations that perfectly symbolize the basic quarter minimization difficulties for series-parallel and nonseries-parallel circuits. those ideas result in useful algorithms that clear up all of the uncomplicated format minimization difficulties precisely, either for a unmarried mobilephone and for a one-dimensional array of such cells. even if some of these format difficulties were solved or partly solved formerly, we current right here the 1st whole suggestions to the entire difficulties of curiosity.